# Board + network boilerplate for the 24-round-screen ClockClock 24 nodes, on a
# Seeed Studio XIAO ESP32-S3 (8 MB PSRAM). Same shape as
# ../digital_clock_clock_24_4_screens/common_base_esp32_s3_xiao.yaml - the pin
# substitutions differ because this build drives three round panels instead of
# two rectangular ones.
#
# Pins are the XIAO's silkscreen labels (ESPHome knows them for this board):
# D0 = GPIO1, D1 = GPIO2, D2 = GPIO3, D3 = GPIO4, D4 = GPIO5, D5 = GPIO6,
# D6 = GPIO43, D7 = GPIO44, D8 = GPIO7, D9 = GPIO8, D10 = GPIO9.

substitutions:
  # SPI bus - shared by all three panels.
  clk_pin: "D8"     # GPIO7,  SCK
  mosi_pin: "D10"   # GPIO9,  MOSI
                    # No MISO: these panels are write-only, and D9 is a
                    # no-connect on the PCB.
  # Shared by all three panels: one DC line and one reset line, so each panel
  # only costs a chip select.
  dc_pin: "D3"      # GPIO4
  reset_pin: "D2"   # GPIO3  - also a strapping pin (JTAG source select); fine
                    #          as a reset output, but don't hold it low at boot
  # One chip select per panel.
  cs_pin_a: "D4"    # GPIO5
  cs_pin_b: "D5"    # GPIO6
  cs_pin_c: "D6"    # GPIO43 - also the ROM's UART0 TX, see the note below
  # No backlight pin: BLK is tied to +3.3 V on the PCB and D7 is a
  # no-connect, so the panels are always at full brightness. D7/GPIO44 is
  # free (it is the ROM's UART0 RX, an input at boot, so nothing contends).
  # Sync bus. D1/GPIO2 is clean: no strapping function, no ROM UART.
  #
  # That matters more than it looks. D6/GPIO43 is the ROM's UART0 TX, and every
  # S3 drives it as an output for the first ~200 ms of a boot - so it must not
  # carry the bus, or a slave would be fighting the master's driver on every
  # power-up. As panel C's chip select above it is harmless: the boot chatter
  # only strobes CS while the panels are still held in reset, and they are
  # initialised from scratch afterwards.
  sync_pin: "D1"    # GPIO2

esp32:
  board: seeed_xiao_esp32s3
  framework:
    type: esp-idf

# The XIAO ESP32-S3 carries 8 MB of octal PSRAM. Unlike the C3 this build used
# to run on, the three LVGL buffers live there and internal RAM is not the
# binding constraint - see the README.
psram:
  mode: octal
  speed: 80MHz

# On the USB console on purpose: the S3's hardware UART0 is D6/D7, and D6 is
# panel C's chip select here.
logger:
  hardware_uart: USB_SERIAL_JTAG

# No `wifi:` / `api:` / `ota:` here on purpose - they live in board_d.yaml (the master).
# A slave takes the time off the UART and needs no network at all, which is the
# whole point of the bus: one board holds the Wi-Fi credentials and the SNTP
# dependency, the other seven are self-contained. The cost is that slaves are
# flashed over USB.
external_components:
  - source: ../components
    components: [lvgl_clock]

# marker only - enables the lvgl_clock widget, takes no options itself.
lvgl_clock:

color:
  - id: cc_hands
    red: 100%
    green: 100%
    blue: 100%
  - id: cc_bg
    red: 0%
    green: 0%
    blue: 0%
  - id: cc_faces  # the little clock's face, drawn behind the hands
    red: 12%
    green: 12%
    blue: 14%

# Heap watch - `block` (largest contiguous chunk) is what a draw buffer needs,
# and it can fail while `free` still looks healthy.
debug:
  update_interval: 60s

sensor:
  - platform: debug
    free:
      name: "Heap Free"
    block:
      name: "Heap Max Block"